1. Technical Field:
The present invention relates in general to data processing and, in particular, to the storage subsystem of a data processing system. Still more particularly, the present invention relates to a processor and data processing system having a hashed and partitioned storage subsystem.
2. Description of the Related Art
In order to capitalize on the high performance processing capability of a state-of-the-art processor 5 core, the storage subsystem of a data processing system must efficiently supply the processor core with large amounts of instructions and data. Conventional data processing systems attempt to satisfy the processor core""s demand for instructions and data by implementing deep cache hierarchies and wide buses capable of operating at high frequency. Although heretofore such strategies have been somewhat effective in staying apace of the demands of the core as processing frequency has increased, such strategies, because of their limited scalability, are by themselves inadequate to meet the data and instruction consumption demands of state-of-the-art and future processor technologies operating at 1 GHz and beyond.
To address the above and other shortcomings of conventional processor and data processing system architectures, the present invention introduces a processor having a hashed and partitioned storage subsystem. A processor includes execution resources, data storage, and an instruction sequencing unit, coupled to the execution resources and the data storage, that supplies instructions within the data storage:to the execution resources. At least one of the execution resources, the data storage, and the instruction sequencing unit is implemented with a plurality of hardware partitions of like function for processing data. The data processed by each hardware partition is assigned according to a selectable hash of addresses associated with the data. In a preferred embodiment, the selectable hash can be altered dynamically during the operation of the processor, for example, in response to detection of an error or a load imbalance between the hardware partitions.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.